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60 dB Range (100 nA to 100 A) Low Cost Logarithmic Converter ADL5306
FEATURES
Optimized for fiber optic photodiode interfacing Measures current over 3 decades Law conformance 0.1 dB from 100 nA to 100 A Single- or dual-supply operation (3 V to 5.5 V total) Full log-ratio capabilities Temperature stable Nominal slope of 10 mV/dB (200 mV/decade) Nominal intercept of 1 nA (set by external resistor) Optional adjustment of slope and intercept Rapid response time for a given current level Miniature 16-lead chip scale package (LFCSP 3 mm x 3 mm) Low power: ~5 mA quiescent current
FUNCTIONAL BLOCK DIAGRAM
VPOS NC VREF 2.5V RREF 200k 0.5V VBIAS 1k Q2 1nF Q1 IPD INPT 1k 1nF VSUM 0.5V 1nF VNEG COMM
03727-0-001
+5V 0.2 log10 I (1nA )
PD
VOUT
20k
80k
BIAS GENERATOR
COMM SCAL BFIN
IREF VBE2
14.2k
I TEMPERATURE LOG COMPENSATION 451 VBE1 6.69k COMM
VLOG
APPLICATIONS
Low cost optical power measurement Wide range baseband logarithmic compression Measurement of current and voltage ratios Optical absorbance measurement
Figure 1. Functional Block Diagram
GENERAL DESCRIPTION
The ADL5306 is a low cost microminiature logarithmic converter optimized for determining optical power in fiber optic systems. The ADL5306 is derived from the AD8304 and AD8305 translinear logarithmic converters. This family of devices provides wide measurement dynamic range in a versatile and easy-to-use form. A single-supply voltage between 3 V and 5.5 V is adequate; dual supplies may optionally be used. Low quiescent current (5 mA typical) permits use in battery-operated applications. IPD, the 100 nA to 100 A input current applied to the INPT pin, is the collector current of an optimally scaled NPN transistor that converts this current to a voltage (VBE) with a precise logarithmic relationship. A second converter is used to handle the reference current, IREF, applied to IREF. These input nodes are biased slightly above ground (0.5 V). This is generally acceptable for photodiode applications where the anode does not need to be grounded. Similarly, this bias voltage is easily accounted for in generating IREF. The logarithmic front end's output is available at VLOG. The basic logarithmic slope at this output is 200 mV/decade (10 mV/dB) nominal; a 60 dB range corresponds to a 600 mV output change. When this voltage (or the buffer output) is applied to an ADC that permits an external reference voltage to be employed, the ADL5306's 2.5 V voltage reference output at VREF can be used to improve scaling accuracy.
The logarithmic intercept (reference current) is nominally positioned at 1 nA by using the externally generated, 100 A IREF current provided by a 200 k resistor connected between VREF, at 2.5 V, and IREF, at 0.5 V. The intercept can be adjusted over a narrow range by varying this resistor. The part can also operate in a log-ratio mode, with limited accuracy, where the numerator and denominator currents are applied to INPT and IREF, respectively. A buffer amplifier is provided to drive substantial loads, raise the basic 10 mV/dB slope, serve as a precision comparator (threshold detector), or implement low-pass filters. Its rail-to-rail output stage can swing to within 100 mV of the positive and negative supply rails, and its peak current-sourcing capacity is 25 mA. A fundamental aspect of translinear logarithmic converters is that small-signal bandwidth falls as current level diminishes, and low frequency noise-spectral density increases. At the 100 nA level, the ADL5306's bandwidth is about 100 kHz; it increases in proportion to IPD up to a maximum of about 10 MHz. The increase in noise level at low currents can be addressed by using a buffer amplifier to realize low-pass filters of up to three poles. The ADL5306 is available in a 16-lead LFCSP package and is specified for operation from-40C to +85C.
Protected by US Patents 4,604,532 and 5,519,308; other patents pending.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 (c) 2003 Analog Devices, Inc. All rights reserved.
ADL5306
TABLE OF CONTENTS
Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 4 Pin Configuration and Pin Function Descriptions...................... 5 Typical Performance Characteristics ............................................. 6 General Structure.............................................................................. 9 Theory............................................................................................ 9 Managing Intercept and Slope .................................................. 10 Response Time and Noise Considerations ............................. 10 Applications..................................................................................... 11 Using a Negative Supply ............................................................ 11 Characterization Methods ........................................................ 12 Evaluation Board ............................................................................ 14 Outline Dimensions ....................................................................... 16 Ordering Guide .......................................................................... 16
REVISION HISTORY
Rev. 0: Initial Version
Rev. 0 | Page 2 of 16
ADL5306 SPECIFICATIONS
Table 1. VP = 5 V, VN = 0, TA = 25C, RREF = 200 k, unless otherwise noted
Parameter INPUT INTERFACE Specified Current Range, IPD Input Current Min/Max Limits Reference Current, IREF, Range Summing Node Voltage Temperature Drift Input Offset Voltage LOGARITHMIC OUTPUT Logarithmic Slope Logarithmic Intercept2 Law Conformance Error Wideband Noise3 Small-Signal Bandwidth3 Maximum Output Voltage Minimum Output Voltage Output Resistance REFERENCE OUTPUT Voltage wrt Ground Maximum Output Current Incremental Output Resistance OUTPUT BUFFER Input Offset Voltage Input Bias Current Incremental Input Resistance Output Range Incremental Output Resistance Peak Source/Sink Current Small-Signal Bandwidth Slew Rate POWER SUPPLY Positive Supply Voltage Quiescent Current Negative Supply Voltage (Optional) -40C < TA < +85C 100 nA < IPD < 100 A IPD > 1 A IPD > 1 A Limited by VN = 0 V 4.375 VREF (Pin 2) -40C < TA < +85C Sourcing (grounded load) Load current < 10 mA BFIN (Pin 10); SCAL (Pin 11); VOUT (Pin 12) Flowing out of Pin 10 or Pin 11 RL = 1 k to ground Load current < 10 mA GAIN = 1 0.2 V to 4.8 V output swing VPOS (Pin 8); VNEG (Pin 6) (VP - VN ) 11 V (VP - VN ) 11 V 2.435 2.4 2.5 20 2 -20 0.4 35 VP - 0.1 0.5 50 15 15 3 -5.5 5 5.4 0 5.5 6.6 +20 2.565 2.6 V V mA mV A M V mA MHz V/s V mA V Conditions INPT (Pin 4), IREF (Pin 3) Flows toward INPT pin Flows toward INPT pin Flows toward IREF pin Internally preset; may be altered by user -40C < TA < +85C VIN - VSUM , VIREF - VSUM VLOG (Pin 9) -40C < TA < +85C Min1 100n 100n 0.46 -20 190 185 0.3 0.1 200 1 0.1 0.7 0.7 1.7 0.01 5 Typ Max1 100 1 100 0.54 +20 210 215 1.7 2.5 0.4 Unit A mA A V mV/C mV mV/dec mV/dec nA nA dB V/Hz MHz V V k
0.5 0.015
5.625
1 2 3
Minimum and maximum specified limits on parameters that are guaranteed but not tested are six sigma values. Other values of logarithmic intercept can be achieved by adjusting RREF. Output noise and incremental bandwidth are functions of input current measured using the output buffer connected for GAIN = 1.
Rev. 0 | Page 3 of 16
ADL5306 ABSOLUTE MAXIMUM RATINGS
Table 2. ADL5306 Absolute Maximum Ratings
Parameter Supply Voltage VP - VN Input Current Internal Power Dissipation JA Maximum Junction Temperature Operating Temperature Range Storage Temperature Range Lead Temperature Range (Soldering 60 sec) Rating 12 V 20 mA 500 mW 135C/W 125C -40C to +85C -65C to +150C 300C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Rev. 0 | Page 4 of 16
ADL5306 PIN CONFIGURATION AND PIN FUNCTION DESCRIPTIONS
COMM COMM COMM COMM
16
15
14
13
NC 1
12 VOUT
VREF 2
11 SCAL
ADL5306
IREF 3
10 BFIN
INPT 4
9 5 6 7 8
VLOG
VSUM VNEG VNEG VPOS
03727-0-002
Figure 2. 16-Lead Leadframe Chip Scale Package (LFCSP)
Table 3. Pin Function Descriptions
Pin No. 1 2 3 4 5 6, 7 8 9 10 11 12 13-16 Mnemonic NC VREF IREF INPT VSUM VNEG VPOS VLOG BFIN SCAL VOUT COMM Function N/A Reference Output Voltage of 2.5 V. Accepts (Sinks) Reference Current IREF. Accepts (Sinks) Photodiode Current IPD. Usually connected to photodiode anode such that photocurrent flows into INPT. Guard Pin. Used to shield the INPT current line and for optional adjustment of the INPT and IREF node potential. Optional Negative Supply, VN. This pin is usually grounded; for details of usage, see the Applications section. Positive Supply, ( VP - VN ) 11 V. Output of the Logarithmic Front End. Buffer Amplifier Noninverting Input. Buffer Amplifier Inverting Input. Buffer Output. Analog Ground.
Rev. 0 | Page 5 of 16
ADL5306 TYPICAL PERFORMANCE CHARACTERISTICS
(VP = 5 V, VN = 0 V, RREF = 200 k, TA = 25C, unless otherwise noted.)
1.2 TA = -40C, 0C, +25C, +70C, +85C VN = 0V 1.0
ERROR (dB (10mV/dB))
1.5 TA = -40C, 0C, +25C, +70C, +85C VN = 0V 1.0 +85C +70C
0.8 VLOG (V)
0.5
0.6
0 +25C
0.4
-0.5 -40C -1.0
0C
0.2
0 10n
100n
1 IPD (A)
10
100
1m
03727-0-003
-1.5 10n
100n
1 IPD (A)
10
100
1m
03727-0-006
Figure 3. VLOG vs. IPD for Multiple Temperatures
1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 10n TA = -40C, 0C, +25C, +70C, +85C VN = 0V
Figure 6. Law Conformance Error vs. IPD (IREF = 10 A) for Multiple Temperatures, Normalized to 25C
1.5 TA = -40C, 0C, +25C, +70C, +85C VN = 0V 1.0 ERROR (dB (10mV/dB))
0.5
+85C
+70C
VLOG (V)
0 +25C -40C -1.0 0C
-0.5
100n
1 IREF (A)
10
100
1m
03727-0-004
-1.5 10n
100n
1 IREF (A)
10
100
1m
03727-0-007
Figure 4. VLOG vs. IREF for Multiple Temperatures
Figure 7. Law Conformance Error vs. IREF (IPD = 10 A) for Multiple Temperatures, Normalized to 25C
0.3
1.6 1.4 1.2 1.0 VLOG (V) 0.8 0.6 0.4 0.2 0 10n 100nA 1A 10A 100A
0.2 ERROR (dB (10mV/dB)) 100A 10A 0 1A -0.1 100nA
0.1
-0.2
100n
1 IPD (A)
10
100
1m
03727-0-005
-0.3 10n
100n
1 IPD (A)
10
100
1m
03727-0-008
Figure 5. VLOG vs. IPD for Multiple Values of IREF (Decade Steps from 10 nA to 1 mA)
Figure 8. Law Conformance Error vs. IPD for Multiple Values of IREF (Decade Steps from 10 nA to 1 mA)
Rev. 0 | Page 6 of 16
ADL5306
1.6 1.4 1.2 1.0
VLOG (V)
0.3
0.2 100nA 100A
ERROR (dB)
0.1 100A 0 1A 10A
10A 0.8 0.6 0.4 0.2 0 10n 1A 100nA
-0.1
-0.2
100n
1 IREF (A)
10
100
1m
03727-0-009
-0.3 10n
100n
1 IREF (A)
10
100
1m
03727-0-012
Figure 9. VLOG vs. IREF for Multiple Values of IPD (Decade Steps from 10 nA to 1 mA)
0.3
Figure 12. Law Conformance Error vs. IREF for Multiple Values of IPD (Decade Steps from 10 nA to 1 mA)
1.2
0.2 ERROR (dB (10mV/dB))
1.0
10A TO 100A: tRISE < 1s, tFALL < 1s 1A TO 10A: tRISE < 1s, tFALL < 5s 100nA TO 1A: tRISE < 5s, tFALL < 20s
0.1 +3V, -0.5V 0 +3V, 0V -0.1 +5V, -5V
+5V, 0V
VOUT (V)
0.8
0.6
0.4
-0.2
0.2
-0.3 10n
100n
1 IPD (A)
10
100
1m
03727-0-010
0 -20
0
20
40
60
80
100
120
140
160
180
03727-0-013
TIME (s)
Figure 10. Law Conformance Error vs. IPD for Various Supply Conditions
Figure 13. Pulse Response: IPD to VOUT (G = 1)
4 3 MEAN + 3 @ -40C
ERROR (dB (10mV/dB))
1.4
TA = -40C, +85C
1.2 1.0 0.8 0.6 0.4 100nA TO 1A: tRISE = 30s, tFALL = 5s 1A TO 10A: tRISE = 5s, tFALL < 1s 10A TO 100A: tRISE = 1s, tFALL < 1s
2 1 0 -1 -2 -3 -4 10n MEAN - 3 @ -40C MEAN 3 @ +85C
VOUT (V)
0.2 0 -20
100n
1 IPD (A)
10
100
1m
03727-0-011
0
20
40
60
80
100
120
140
160
180
03727-0-014
TIME (s)
Figure 11. VINPT - VSUM vs. IPD
Figure 14. Pulse Response: IREF to VOUT (G = 1)
Rev. 0 | Page 7 of 16
ADL5306
10 5 NORMALIZED RESPONSE (dB) 0 -5 -10 -15 10A -20 -25 -30 -35 -40 100 1k 10k 100k FREQUENCY (Hz) 1M 10M 100M
03727-0-015
5
100nA
0
100A
NORMALIZED RESPONSE (dB)
-5
Av = 5
Av = 1
-10 Av = 2 Av = 2.5 -20
-15
1A
-25 10k
100k
1M FREQUENCY (Hz)
10M
100M
03727-0-018
Figure 15. Small-Signal AC Response (5% Sine Modulation), from IPD to VOUT (G = 1) for IPD in Decade Steps from 10 nA to 1 mA
10 5 NORMALIZED RESPONSE (dB) 0 -5 -10 -15 10A -20 -25 -30 -35 -40 100 1k 10k 100k FREQUENCY (Hz) 1M 10M 100M
03727-0-016
Figure 18. Small-Signal AC Response of the Buffer for Various Closed-Loop Gains (RL = 1 k, CL < 2 pF)
2.0
100nA 100A VOS DRIFT (mV)
1.5 1.0 MEAN + 3 0.5 0
-0.5 MEAN - 3 -1.0 -1.5 -2.0 -40 -30 -20 -10
1A
0
10
20
30
40
50
60
70
80 90
03727-0-019
TEMPERATURE (C)
Figure 16. Small-Signal AC Response (5% Sine Modulation), from IREF to VOUT (G = 1) for IREF in Decade Steps from 10 nA to 1 mA
100
Figure 19. Buffer Input Offset Drift vs. Temperature (3 to Either Side of Mean)
6
5
10 100nA
4
Vrms/ Hz
1A
mVrms
100A
1
3
10A 0.1
2
1
0.01 100
1k
10k
100k
1M
10M
03727-0-017
0 10n
100n
1 IPD (A)
10
100
1m
03727-0-020
FREQUENCY (Hz)
Figure 17. Spot Noise Spectral Density at VOUT (G = 1) vs. Frequency for IPD in Decade Steps from 10 nA to 1 mA
Figure 20. Total Wideband Noise Voltage at VOUT vs. IPD (G = 1)
Rev. 0 | Page 8 of 16
ADL5306 GENERAL STRUCTURE
The ADL5306 addresses a wide variety of interfacing conditions to meet the needs of fiber optic supervisory systems, and is useful in many nonoptical applications. This section explains the structure of this unique style of translinear log amp. The simplified schematic in Figure 21 shows the key elements.
BIAS GENERATOR PHOTODIODE 2.5V INPUT CURRENT 80k IPD INPT 0.5V VSUM IREF VREF IREF 20k COMM 0.5V 2.5V 0.5V Q1 VBE1 Q2 VBE2 6.69k COMM
03727-0-021
THEORY
The base-emitter voltage of a BJT (bipolar junction transistor) can be expressed by the following equation, which immediately shows its basic logarithmic nature: VBE = kT/q ln(IC / IS) (1)
VBE1 VBE2
TEMPERATURE COMPENSATION (SUBTRACT AND DIVIDE BY TK) 44A/dec 14.2k 451 VLOG
where: IC is the collector current IS is a scaling current, typically only 10-17 A kT/q is the thermal voltage, proportional to absolute temperature (PTAT), and is 25.85 mV at 300 K. IS is never precisely defined and exhibits an even stronger temperature dependence, varying by a factor of roughly a billion between -35C and +85C. Thus, to make use of the BJT as an accurate logarithmic element, both of these temperaturedependencies must be eliminated. The difference between the base-emitter voltages of a matched pair of BJTs, one operating at the photodiode current IPD and the other operating at a reference current IREF, can be written as VBE1 - VBE2 = kT/q ln(IPD / IS) - kT/q ln(IREF / IS) = ln(10) kT/q log10(IPD / IREF) = 59.5 mV log10(IPD / IREF) (T = 300 K) The uncertain, temperature-dependent saturation current, IS, that appears in Equation 1 has therefore been eliminated. To eliminate the temperature variation of kT/q, this difference voltage is processed by what is essentially an analog divider. Effectively, it puts a variable under Equation 2. The output of this process, which also involves a conversion from voltage mode to current mode, is an intermediate, temperaturecorrected current: ILOG = IY log10(IPD / IREF) (3) (2)
VNEG (NORMALLY GROUNDED)
Figure 21. Simplified Schematic
The photodiode current IPD is received at Pin INPT. The voltage at this node is essentially equal to the voltage on the two adjacent guard pins, VSUM and IREF, due to the low offset voltage of the JFET op amp. Transistor Q1 converts IPD to a corresponding logarithmic voltage, as shown in Equation 1. A finite positive value of VSUM is needed to bias the collector of Q1 for the usual case of a single-supply voltage. This is internally set to 0.5 V, one fifth of the 2.5 V reference voltage appearing on Pin VREF. The resistance at the VSUM pin is nominally 16 k; this voltage is not intended as a general bias source. The ADL5306 also supports the use of an optional negative supply voltage, VN , at Pin VNEG. When VN is -0.5 V or more negative, VSUM may be connected to ground; thus, INPT and IREF assume this potential. This allows operation as a voltageinput logarithmic converter by the inclusion of a series resistor at either or both inputs. Note that the resistor setting, IREF, will need to be adjusted to maintain the intercept value. It should also be noted that the collector-emitter voltages of Q1 and Q2 are now the full VN, and effects due to self-heating will cause errors at large input currents. The input-dependent VBE1 of Q1 is compared with the reference VBE2 of a second transistor, Q2, operating at IREF. This is generated externally to a recommended value of 10 A. However, other values over a several-decade range can be used with a slight degradation in law conformance (see Figure 8).
where IY is an accurate, temperature-stable scaling current that determines the slope of the function (change in current per decade). For the ADL5306, IY is 44 A, resulting in a temperature-independent slope of 44 A/decade for all values of IPD and IREF . This current is subsequently converted back to a voltage-mode output, VLOG, scaled 200 mV/decade.
Rev. 0 | Page 9 of 16
ADL5306
It is apparent that this output should be zero for IPD = IREF, and would need to swing negative for smaller values of input current. To avoid this, IREF would need to be as small as the smallest value of IPD. In the ADL5306, an internal offset voltage is added to VLOG to shift it upward by 0.8 V. This moves the intercept to the left by four decades, from 10 A to 1 nA: ILOG = IY log10(IPD / IINTC) (4)
MANAGING INTERCEPT AND SLOPE
As previously noted, the internally generated 2.5 V bias combines with the on-chip resistors to introduce an accurate offset voltage of 0.8 V at the VLOG pin, equivalent to four decades. This results in a logarithmic transfer function that can be written as VLOG = VY log10 (104 x IPD / IREF)= VY log10 (IPD / IINTC) where IINTC = IREF /104 Thus, the effective intercept current, IINTC, is only one tenthousandth of IREF, corresponding to 10 nA when using the recommended value of IREF = 100 A. The slope can be reduced by attaching a resistor to the VLOG pin. This is strongly discouraged because the on-chip resistors will not ratio correctly to the added resistance. Also, it is rare that one would wish to lower the basic slope of 10 mV/dB; if this is necessary, it should be done at the low impedance output of the buffer, which is provided to avoid such miscalibration and allow higher slopes to be used. The ADL5306 buffer is essentially an uncommitted op amp with rail-to-rail output swing, good load driving capabilities, and a unity-gain bandwidth of >20 MHz. In addition to allowing the introduction of gain using standard feedback networks, thereby increasing the slope voltage, VY, the buffer can be used to implement multipole low-pass filters, threshold detectors, and a variety of other functions. For more details, see the AD8304 Data Sheet. (6)
where IINTC is the operational / value of the intercept current. Since values of IPD < IINTC result in a negative VLOG, a negative supply of sufficient value is required to accommodate this situation (discussed later). The voltage VLOG is generated by applying ILOG to an internal resistance of 4.55 k, formed by the parallel combination of a 6.69 k resistor to ground and the 14.2 k resistor to the internal 2.5 V reference. At the VLOG pin, the output current ILOG generates a voltage of VLOG = ILOG x 4.55 k = 44 A x 4.55 k x log10 (IPD / IREF) = VY log10 (IPD / IREF) where VY = 200 mV/decade or 10 mV/dB. Note that any resistive loading on VLOG will lower this slope and will result in an overall scaling uncertainty due to the variability of the onchip resistors. Consequently, this practice is not recommended. VLOG may also swing below ground when dual supplies (VP and VN) are used. When VN = -0.5 V or more negative, the input pins INPT and IREF may be positioned at ground level simply by grounding VSUM. (5)
RESPONSE TIME AND NOISE CONSIDERATIONS
The response time and output noise of the ADL5306 are fundamentally a function of the signal current IPD. For small currents, the bandwidth is proportional to IPD. The output's low frequency voltage-noise spectral density is a function of IPD, and increases for small values of IREF. For details of noise and bandwidth performance of translinear log amps, see the AD8304 Data Sheet.
Rev. 0 | Page 10 of 16
ADL5306 APPLICATIONS
The ADL5306 is easy to use in optical supervisory systems and in similar situations where a wide-ranging current is to be converted to its logarithmic equivalent (i.e., represented in decibel terms). Basic connections for measuring a single current input are shown in Figure 22, which includes various nonessential components, as will be explained.
VPOS NC VREF 2.5V RREF 200k 20k 0.5V IREF VBE2 I TEMPERATURE LOG COMPENSATION VBE1 6.69k COMM 0.5V 1nF VNEG COMM
03727-0-022
frequency is 3.2 kHz. Such filtering is useful in minimizing the output noise, particularly when IPD is small. Multipole filters are more effective in reducing the total noise. For examples, see the AD8304 Data Sheet. The dynamic response of this overall input system is influenced by the external RC networks connected from the two inputs (INPT, IREF) to ground. These are required to stabilize the input systems over the full current range. The bandwidth changes with the input current due to the widely varying pole frequency. The RC network adds a zero to the input system to ensure stability over the full range of input current levels. The network values shown in Figure 22 will usually suffice, but some experimentation may be necessary when the photodiode's capacitance is high. Although the two current inputs are similar, some care is needed to operate the reference input at extremes of current (<100 nA) and temperature (<0C). Modifying the RC network to 4.7 nF and 2 k will allow operation to -40C at 10 nA. By inspecting the transient response to perturbations in IREF at representative current levels, the capacitor value can be adjusted to provide fast rise and fall times with acceptable settling. To fine-tune the network zero, the resistor value should be adjusted.
+5V 0.5 log10 I ( 1nA )
PD
VOUT
80k COMM
BIAS GENERATOR 12k
VBIAS 1k
14.2k Q2
SCAL BFIN VLOG 451
1nF Q1 IPD INPT 1k 1nF VSUM
CFLT 10nF
8k
Figure 22. Basic Connections for Fixed Intercept Use
The 2 V difference in voltage between VREF and INPT, in conjunction with the external 200 k resistor RREF, provides a reference current IREF of 100 A into Pin IREF. The internal reference raises the voltage at VLOG by 0.8 V, effectively lowering the intercept current IINTC by a factor of 104 to position it at 1 nA. Any temperature variation in RREF must be taken into account when estimating the stability of the intercept. Also, the overall noise will increase when using very low values of IREF. In fixed-intercept applications, there is little benefit in using a large reference current, since this only compresses the low current end of the dynamic range when operated from a single supply, shown here as 5 V. The capacitor between VSUM and ground is recommended to minimize the noise on this node and to help provide a clean reference current. Since the basic scaling at VLOG is 0.2 V/dec and a swing of 4 V at the buffer output would therefore correspond to 20 decades, it will often be useful to raise the slope to make better use of the rail-to-rail voltage range. For illustrative purposes, the circuit in Figure 22 provides an overall slope of 0.5 V/dec (25 mV/dB). Thus, using IREF = 100 A, VLOG runs from 0.2 V at IPD = 100 nA to 0.8 V at IPD = 100 A. The buffer output runs from 0.5 V to 2.0 V, corresponding to a dynamic range of 60 dB electrical (30 dB optical) power. The optional capacitor from VLOG to ground forms a singlepole low-pass filter in combination with the 4.55 k resistance at this pin. For example, using a CFLT of 10 nF, the -3 dB corner
USING A NEGATIVE SUPPLY
Most applications of the ADL5306 require only a single supply of 3.0 V to 5.5 V. However, to provide further versatility, dual supplies may be employed, as illustrated in Figure 23.
VPOS NC VREF 2.5V RREF 200k 20k 80k 0.5 log10 BIAS GENERATOR 12k +5V I (1nA )
PD
VOUT
0.5V COMM IREF VBE2 I TEMPERATURE LOG COMPENSATION VBE1 6.69k COMM 0.5V VF VNEG Iq + Isig Isig = IPD + IREF RS VN VN - VF Iq + Isigmax VSUM - VF -0.5V COMM VLOG 451
VBIAS 1k
14.2k Q2
SCAL BFIN
1nF Q1 IPD INPT 1k 1nF VSUM
CFLT 10nF
8k
C1
03727-0-023
Figure 23. Negative Supply Application
Rev. 0 | Page 11 of 16
ADL5306
The use of a negative supply, VN, allows the summing node to be placed at ground level whenever the input transistor (Q1 in Figure 1) has a sufficiently negative bias on its emitter. When VN = -0.5 V, the VCE of Q1 and Q2 will be the same value as in the default case when VSUM is grounded. This bias need not be accurate, and a poorly defined source can be used. However, the source must be able to support the quiescent current as well as the INPT and IREF signal current. For example, it may be convenient to utilize a forward-biased junction voltage of about 0.7 V or a Schottky barrier voltage of a little over 0.5 V. With the summing node at ground, the ADL5306 may now be used as a voltage-input log amp, at either the numerator input INPT or the denominator input IREF by inserting a suitably scaled resistor from the voltage source to the relevant pin. The overall accuracy for small input voltages is limited by the voltage offset at the inputs of the JFET op amps. The use of a negative supply also allows the output to swing below ground, thereby allowing the intercept to correspond to a midrange value of IPD. However, the voltage VLOG remains referenced to the ACOM pin, and while VLOG does not swing negative for default operating conditions, it is free to do so. Thus, adding a resistor from VLOG to the negative supply lowers all values of VLOG, which raises the intercept. The disadvantage of this method is that the slope is reduced by the shunting of the external resistor, and the poorly defined ratio of on-chip and off-chip resistance causes errors in both the slope and intercept. A more accurate method for repositioning the intercept follows.
VREF KEITHLEY 236 IREF VNEG VPOS VOUT
KEITHLEY 236
CHARACTERIZATION BFIN BOARD VLOG INPT VSUM RIBBON CABLE
ADL5306
TRIAX CONNECTORS (SIGNAL - INPT AND IREF GUARD - VSUM SHIELD - GROUND)
DC MATRIX / DC SUPPLIES / DMM
03727-0-024
Figure 24. Primary Characterization Setup
The primary characterization setup shown in Figure 24 is used to measure VREF, the static (dc) performance, logarithmic conformance, slope and intercept, the voltages appearing at Pins VSUM, INPT, and IREF, and the buffer offset and VREF drift with temperature. In some cases, a fixed resistor between Pins VREF and IREF was used in place of a precision current source. For the dynamic tests, including noise and bandwidth measurements, more specialized setups are required. This includes close attention to the input stabilizing networks; for example, to ensure stable operation over the full current range of IREF and temperature extremes, filter components C1 = 4.7 nF and R13 = 2 k are used at Pin IREF to ground.
NETWORK ANALYZER OUTPUT INPUT R INPUT A INPUT B
HP3577A
CHARACTERIZATION METHODS
During the characterization of the ADL5306, the device was treated as a precision current-input logarithmic converter, because it is impractical to generate accurate photocurrents by illuminating a photodiode. The test currents were generated by using either a well-calibrated current source, such as the Keithley 236, or a high value resistor from a voltage source to the input pin. Great care is needed when using very small input currents. For example, the triax output connection from the current generator was used with the guard tied to VSUM. The input trace on the PC board was guarded by connecting adjacent traces to VSUM. These measures are needed to minimize the risk of leakage current paths. With 0.5 V as the nominal bias on the INPT pin, a leakage-path resistance of 1 G to ground would subtract 0.5 nA from the input, which amounts to a -0.44 dB error for a 10 nA source current. Additionally, the very high output resistance at the input pins and the long cables commonly needed during characterization allow 60 Hz and RF emissions to introduce substantial measurement errors. Careful guarding techniques are essential to reducing the pickup of these spurious signals.
+IN EVALUATION BOARD
B
16 15 14 13 COMM COMM COMM COMM
AD8138
1 NC
A BNC-T
VOUT 12
2 VREF 3 IREF 4 INPT
SCAL 11
ADL5306
AD8138 PROVIDES DC OFFSET
BFIN 10
VLOG 9
VSUM VNEG VNEG VPOS 5 6 7 8 +VS 0.1F
03727-0-025
Figure 25. Configuration for Buffer Amplifier Bandwidth Measurement
Figure 25 shows the configuration used to measure the buffer amplifier bandwidth. The AD8138 evaluation board includes provisions to offset VLOG at the buffer input, allowing measurements over the full range of IPD using a single supply. The network analyzer input impedances are set to 1 M.
Rev. 0 | Page 12 of 16
ADL5306
NETWORK ANALYZER OUTPUT INPUT R INPUT A INPUT B
HP3577A
The configuration of Figure 27 is used to measure the noise performance. Batteries provide both the supply voltage and the input current in order to minimize the introduction of spurious noise and ground loop effects. The entire evaluation system, including the current setting resistors, is mounted in a closed aluminum enclosure to provide additional shielding to external noise sources.
VOUT 12 SCAL 11
POWER SPLITTER
16 15 14 13 COMM COMM COMM COMM
1 NC 2 VREF
LeCROY 9210
9213
CH A
TDS5104
CH 1
+IN EVALUATION BOARD
B
R2
AD8138
ADL5306
3 IREF
BFIN 10 VLOG 9
A
R1
4 INPT
1k 1nF
1k 1nF
VSUM VNEG VNEG VPOS 5 6 7 8 +VS 0.1F
03727-0-026
16 15 14 13 COMM COMM COMM COMM
1 NC 2 VREF
VOUT 12
SCAL 11
Figure 26. Configuration for Logarithmic Amplifier Bandwidth Measurement
R1
200k
ADL5306
3 IREF 4 INPT
BFIN 10
VLOG 9
Figure 26 shows the configuration used for frequency response measurements of the logarithmic amplifier section. The AD8138 output is offset to 1.5 V dc and modulated to a depth of 5% at frequency. R1 is chosen (over a wide range of values up to 1.0 G) to provide IPD. The buffer is used to deload VLOG.
50k
1k 1nF
1k 1nF
VSUM VNEG VNEG VPOS 5 6 7 8 +VS 0.1F
03727-0-028
Figure 28. Configuration for Logarithmic Amplifier Pulse Response Measurement
HP89410A
SOURCE TRIGGER CHANNEL 1 CHANNEL 2
16 15 14 13 COMM COMM COMM COMM
1 NC 2 VREF
200k
VOUT 12 SCAL 11
Figure 28 shows the setup used to make the pulse response measurements. As with the bandwidth measurement, VLOG is connected directly to BFIN and the buffer amplifier is configured for a gain of 1. The buffer's output is connected through a short cable to the TDS5104 scope, with the input impedance set to 1 M. The LeCroy's output is offset to create the initial pedestal current for a given R1 value. The pulse then creates a 1-decade current step.
ADL5306
3 IREF
BFIN 10 VLOG 9
R1
4 INPT
ALKALINE "D" CELL
1k 1nF
1k 1nF
VSUM VNEG VNEG VPOS 5 6 7 8
0.1F
ALKALINE "D" CELL
03727-0-027
Figure 27. Configuration for Noise Spectral Density Measurement
Rev. 0 | Page 13 of 16
ADL5306 EVALUATION BOARD
An evaluation board is available for the ADL5306, the schematic of which is shown in 29. It can be configured for a wide variety of experiments. The buffer gain is factory-set to unity, providing Table 4. Evaluation Board Configuration Options
Component P1 P2, R8, R9, R10, R18 Function Supply Interface. Provides access to supply pins VNEG, COMM, and VPOS. Monitor Interface. By adding 0 resistors to R8, R9, R10, and R18, the VREF, VSUM, VOUT, and VLOG pin voltages can be monitored using a high impedance probe. Buffer Amplifier/Output Interface. The logarithmic slope of the ADL5306 can be altered using the buffer's gainsetting resistors, R2 and R3. R4, R6, R11, R14, C2, C7, C9, and C10 are provided for a variety of filtering applications. Default Conditions P1 = Installed P2 = Not Installed R8 = R9 = R10 = Open (Size 0603) R18 = Open (Size 0603) R2 = R6 = 0 (Size 0603) R3 = R4 = Open (Size 0603) R11 = R14 = 0 (Size 0603) C2 = C7 = Open (Size 0603) C9 = C10 = Open (Size 0603) VLOG = VOUT = Installed R1 = 200 k (Size 0603) R19 = 0 (Size 0603) C3 = C4 = 0.01 F (Size 0603) C5 = C6 = 0.1 F (Size 0603) R12 = R15 = 0 (Size 0603) C11 = 1 nF (Size 0603) R13 = R16 = 1 k (Size 0603) C1 = C8 = 1 nF (Size 0603) IREF = INPT = Installed PD = Not Installed LK1 = Installed R5 = Open (Size 0603)
a slope of 200 mV/dec, and the intercept is set to 1 nA. Table 4 describes the various configuration options.
R2, R3, R4, R6, R11, R14, C2, C7, C9, C10
R1, R19
R12, R15, C3, C4, C5, C6
Intercept Adjustment. The voltage dropped across resistor R1 determines the intercept reference current, nominally set to 10 A using a 200 k 1% resistor. Supply Decoupling
C11 R13, R16, C1, C8 IREF, INPT, PD, LK1, R5
Filtering VSUM Input Compensation. Provides essential HF compensation at the input pins, INPT and IREF. Input Interface. The test board is configured to accept a current through the SMA connector labeled INPT. An SC style packaged photodiode can be used in place of the INPT SMA for optical interfacing. By removing R1 and adding a 0 short for R5, a second current can be applied to the IREF input (also SMA) for evaluating the ADL5306 in log-ratio applications. SC Style Photodiode
J1
J1 = Open
Rev. 0 | Page 14 of 16
ADL5306
R10
16 15 14 13 COMM COMM COMM COMM
1 NC VREF IREF SC-STYLE PD 1 2 3 INPT R18
OPEN
OPEN
VOUT
VOUT 12 SCAL 11
R14 R2 0 R3
OPEN
R5
OPEN
R19 2 VREF R1 0 200k IREF 1% 3 IREF R13 1k C1 1nF IPD 4 INPT
C9
OPEN
C2
OPEN
R4
0
VOUT
OPEN
ADL5306
BFIN 10 VLOG 9 C7
R6 0
R8
OPEN
VLOG VLOG
R11 C10
OPEN
VSUM VNEG VNEG VPOS 5 6 7 8
0
OPEN
C3 0.01F
C4 0.01F
AGND VOUT
1 2 3 4 5 P2
03727-0-029
LK1 C11
R9 OPEN R16 1nF VSUM C8
1k 1nF
VREF C6 0.1F VNEG AGND C5 0.1F VSUM VLOG
1
2
3 P1
VPOS
Figure 29. Evaluation Board Schematic
03727-0-030
03727-0-031
Figure 30. Component Side Layout
Figure 31. Component Side Silkscreen
Rev. 0 | Page 15 of 16
ADL5306 OUTLINE DIMENSIONS
3.00 BSC SQ 0.45 PIN 1 INDICATOR TOP VIEW 2.75 BSC SQ 0.50 BSC 12MAX 1.00 0.90 0.80 SEATING PLANE 0.30 0.23 0.18 0.80 MAX 0.65 NOM 0.05 MAX 0.01 NOM 0.20 REF 1.50 REF
BOTTOM VIEW
0.60 MAX
0.50 0.40 0.30 PIN 1 INDICATOR
1 2
1.45 1.30 SQ 1.15 0.25 MIN
COMPLIANT TO JEDEC STANDARDS MO-220-VEED-2
Figure 32. 16-Lead Leadframe Chip Scale Package [LFCSP] (CP-16) Dimensions shown in millimeters
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
ORDERING GUIDE
ADL5306 Products ADL5306ACP2 ADL5306ACP-R2 ADL5306ACP-REEL7 ADL5306-EVAL Temperature Package -40C to +85C -40C to +85C -40C to +85C Package Description 16-Lead LFCSP Tape and Reel 7" Tape and Reel Evaluation Board Package Outline CP-16 CP-16 CP-16 Branding1 JSA JSA JSA
1
Branding is as follows: Line 1--Logo Line 2--JSA Line 3--K (Date Code). Date code is in YWW format. 2 Contact factory for availability.
(c) 2003 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective companies. C03727-0-7/03(0)
Rev. 0 | Page 16 of 16
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